Lost GPIO Pins P4RX+/-/TX+/- P0RX+/-/TX+/- G25: How do we use them like GPIOs?

Technical Support for Routers
1

What are these Pins used for ?
How can we use them for Bitbanging like GPIO ?


# P4RX+ ??   p36 
# P4RX- ??   p37 
# P4TX+ ??   p38 
# P4TX+ ??   p39 
                
# P0RX+ ??   p41 
# P0RX+ ??   p42 
# P0TX+ ??   p43 
# P0TX+ ??   p44

And,
Where is GPIO25 pin# ?

2

These are for Ethernet, WAN and LAN and cannot be used like GPIO.

in the datasheet of 9331, there is no GPIO25.

3

Is there any way to use the P0 and P4 with alternate function ?

4

I don’t think it is possible.

5

Are there Registers for these Pins ?

6

Sorry for the very, very late reply… After checking I can verify that there is no way to use these pins for anything besides their original purpose: for Ethernet. There’s no way to control them directly, the only pins that have a pin-to-register mapping are the GPIOs. The AR9331 is rather interesting because they really seem to have removed everything except what you might want for a Wi-fi device with Ethernet connectivity. --Even the amount of RAM is capped at 64MB for whatever reason. The hardware SPI is also limited and appears to only support use with specific flash devices for booting, with no provisions for connecting up other non-flash devices. Maybe someone else can double-check this, but it doesn’t look like it’s possible to use the SPI hardware for anything else.

It sure would be great to see a second-generation of Domino devices made with more hacker-friendly features at the same low price (Obviously using some other chip than an AR9331); things like SPI, I2C, more RAM, higher speed/multiple cores, memory-mapped I/O, and more GPIOs would be very welcome! The Domino got a lot of things right as far as price, relatively low power consumption, size, and network connections are concerned, it’s just too bad the CPU is so limited for other purposes. I suppose someone who was motivated enough could make an add-on board specifically for the Domino Pi that implemented things like SPI, I2C, and additional GPIO (Maybe in a CPLD or small FPGA?), but it doesn’t seem likely. I personally have already run into problems with the number of GPIOs and it’s painful having to spread a data bus across non-sequential GPIOs.

-Larry